WebJun 9, 2007 · This paper introduces the flattened butterfly, a cost-efficient topology for high-radix networks. On benign (load-balanced) traffic, the flattened butterfly approaches the cost/performance of a butterfly network and has roughly half the cost of a comparable performance Clos network.The advantage over the Clos is achieved by eliminating ... WebJun 16, 2010 · The flattened butterfly is known to be a cost efficient topology for high-radix networks. Because of its inherent path diversity, it is able to provide comparable …
2-Dilated flattened butterfly: A nonblocking switching …
WebOct 28, 2024 · The present work proposes an NoC topology taking into account the above design considerations. Rigorous experimentation is done with prevalent counterparts like mesh, torus, flattened-butterfly, butterfly-fat-tree, etc. Low network diameter and sufficient path diversity come up with a minimum of 38% latency improvement among all the cases. WebIf nonminimal routing is exploited, path diversity similar to a folded-Clos topology can be achieved. An example is shown in Figure5.3(b) where the packet is first routed to an intermediate router (R13) before routing to its destination. In this section, we describe different routing algorithms on the flattened butterfly topology. 46 5. ROUTING chris creighton coaching record
A scalable NoC topology targeting network performance
WebIn this work, we propose the use of high-radix networks in on-chip networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip topologies. WebSep 15, 2011 · To take full advantage of these high radix routers, a cost-efficient topology known as flattened butterfly [5] has been proposed. A flattened butterfly is derived … WebFlattened Butterfly Topology for On-Chip Networks. Abstract: With the trend towards increasing number of cores in a multicore processors, the on-chip network that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip networks and describe how the flattened butterfly topology can be ... chris creighton indot